Search results for: Timo Viitanen

Items from 1 to 20 out of 21 results

article

ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA

Joost Hoozemans, Jeroen Straten, Timo Viitanen, Aleksi Tervo, more

Journal of Signal Processing Systems > 2019 > 91 > 1 > 61-73

The proliferation of processing hardware alternatives allows developers to use various customized computing platforms to run their applications in an optimal way. However, porting application code on custom hardware requires a lot of development and porting effort. This paper describes a heterogeneous computational platform (the ALMARVI execution platform) comprising of multiple communicating processors...

article

Instruction Fetch Energy Reduction with Biased SRAMs

Joonas Multanen, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala

Journal of Signal Processing Systems > 2018 > 90 > 11 > 1519-1532

Especially in programmable processors, energy consumption of integrated memories can become a limiting design factor due to thermal dissipation power constraints and limited battery capacity. Consequently, contemporary improvement efforts on memory technologies are focusing more on the energy-efficiency aspects, which has resulted in biased CMOS SRAM cells that increase energy efficiency by favoring...

article

Variable Length Instruction Compression on Transport Triggered Architectures

Timo Viitanen, Janne Helkala, Heikki Kultala, Pekka Jääskeläinen, more

International Journal of Parallel Programming > 2018 > 46 > 6 > 1283-1303

The memories used for embedded microprocessor devices consume a large portion of the system’s power. The power dissipation of the instruction memory can be reduced by using code compression methods, which may require the use of variable length instruction formats in the processor. The power-efficient design of variable length instruction fetch and decode is challenging for static multiple-issue processors,...

chapter

Design and implementation of a multi-mode harris corner detector architecture

Jingui Li, Timo Viitanen, Lin Li, Jarmo Takala, more

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) > 1 - 6

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

In this paper, we present a configurable architecture for corner detection in images based on the well-known Harris corner detection algorithm, and we demonstrate a field programmable gate array (FPGA) implementation of the proposed architecture. Our architecture is designed to be configurable across diverse operational trade-offs, which makes it useful for integration into a wide variety of application...

article

Hardware design methodology using lightweight dataflow and its integration with low power techniques

Tiziana Fanni, Lin Li, Timo Viitanen, Carlo Sau, more

Journal of Systems Architecture > 2017 > 78 > C > 15-29

Dataflow models of computation are capable of providing high-level descriptions for hardware and software components and systems, facilitating efficient processes for system-level design. The modularity and parallelism of dataflow representations make them suitable for key aspects of design exploration and optimization, such as efficient scheduling, task synchronization, memory and power management...

article

A 5.3 pJ/op approximate TTA VLIW tailored for machine learning

Jukka Teittinen, Markus Hiienkari, Indrė Žliobaitė, Jaakko Hollmen, more

Microelectronics Journal > 2017 > 61 > C > 106-113

To achieve energy efficiency in the Internet-of-Things (IoT), more intelligence is required in the wireless IoT nodes. Otherwise, the energy required by the wireless communication of raw sensor data will prohibit battery lifetime, the backbone of IoT. One option to achive this intelligence is to implement a variety of machine learning algorithms on the IoT sensor instead of the cloud. Shown here is...

chapter

OpenCL programmable exposed datapath high performance low-power image signal processor

Joonas Multanen, Heikki Kultala, Matias Koskela, Timo Viitanen, more

2016 IEEE Nordic Circuits and Systems Conference (NORCAS) > 1 - 6

2016 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

Sophisticated computational imaging algorithms require both high performance and good energy-efficiency when executed on mobile devices. Recent trend has been to exploit the abundant data-level parallelism found in general purpose programmable GPUs. However, for low-power mobile use cases, generic GPUs consume excessive amounts of power. This paper proposes a programmable computational imaging processor...

chapter

Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies

Joonas Multanen, Timo Viitanen, Pekka Jaaskelainen, Jarmo Takala

2016 IEEE International Workshop on Signal Processing Systems (SiPS) > 63 - 68

2016 IEEE International Workshop on Signal Processing Systems (SiPS)

Pervasive computing calls for ultra-low-power devices to extend the battery life enough to enable usability in everyday life. Especially in devices involving programmable processors, the energy consumption of integrated memories often plays a critical role. Consequently, contemporary memory technologies focus more on the energy-efficiency aspects with new custom CMOS SRAM cells with tailored energy...

chapter

Low power design methodology for signal processing systems using lightweight dataflow techniques

Lin Li, Tiziana Fanni, Timo Viitanen, Renjie Xie, more

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) > 82 - 89

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)

Dataflow modeling techniques facilitate many aspects of design exploration and optimization for signal processing systems, such as efficient scheduling, memory management, and task synchronization. The lightweight dataflow (LWDF) programming methodology provides an abstract programming model that supports dataflow-based design and implementation of signal processing hardware and software components...

chapter

Improved image quality in fast inpainting with omnidirectional filling

Ossi Hirvola, Timo Viitanen, Vicky Sintunata, Terumasa Aoki

2016 International Conference on Image, Vision and Computing (ICIVC) > 31 - 35

2016 International Conference on Image, Vision and Computing (ICIVC)

Image inpainting is an active research field of image processing. Previous inpainting methods often require a long computational time to give sufficient results, especially due to the extensive search process of exemplar-based methods. This work improves a previous fast inpainting method based on local similarity, which achieves runtimes measured in tens of milliseconds per image, but often results...

article

Improving Code Density with Variable Length Encoding Aware Instruction Scheduling

Heikki Kultala, Timo Viitanen, Pekka Jääskeläinen, Janne Helkala, more

Journal of Signal Processing Systems > 2016 > 84 > 3 > 435-446

Variable length encoding can considerably decrease code size in VLIW processors by reducing the number of bits wasted on encoding No Operations(NOPs). A processor may have different instruction templates where different execution slots are implicitly NOPs, but all combinations of NOPs may not be supported by the instruction templates. The efficiency of the NOP encoding can be improved by the compiler...

chapter

Rapid customization of image processors using Halide

Ville Korhonen, Pekka Jaaskelainen, Matias Koskela, Timo Viitanen, more

2015 IEEE Global Conference on Signal and Information Processing (GlobalSIP) > 629 - 633

2015 IEEE Global Conference on Signal and Information Processing (GlobalSIP)

Image processing applications typically involve data-oriented kernels with limited control divergence. In order to efficiently exploit the data level parallelism, image processors include SIMD instructions and other parallel computation resources. Generic processors that can be purchased off-the-shelf are adequate for most of the use scenarios of image processing. However, especially with embedded...

chapter

Impact of operand sharing to the processor energy efficiency

Heikki Kultala, Joonas Multanen, Pekka Jaaskelainen, Timo Viitanen, more

2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS) > 1 - 6

2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS)

Transport triggered architecture processors may have function unit input registers, which allow operands to be written to function units earlier than the clock cycle where the operation begins execution. An operand used in consecutive operations may be written only once, saving register file accesses and internal bus traffic. This optimization is called operand sharing. In this paper, the effectiveness...

chapter

Power optimizations for transport triggered SIMD processors

Joonas Multanen, Timo Viitanen, Henry Linjamaki, Heikki Kultala, more

2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) > 303 - 309

2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

Power consumption in modern processor design is a key aspect. Optimizing the processor for power leads to direct savings in battery energy consumption in case of mobile devices. At the same time, many mobile applications demand high computational performance. In case of large scale computing, low power compute devices help in thermal design and in reducing the electricity bill. This paper presents...

article

Code Density and Energy Efficiency of Exposed Datapath Architectures

Pekka Jääskeläinen, Heikki Kultala, Timo Viitanen, Jarmo Takala

Journal of Signal Processing Systems > 2015 > 80 > 1 > 49-64

Exposing details of the processor datapath to the programmer is motivated by improvements in the energy efficiency and the simplification of the microarchitecture. However, an instruction format that can control the data path in a more explicit manner requires more expressiveness when compared to an instruction format that implements more of the control logic in the processor hardware and presents...

chapter

Compiler optimizations for code density of variable length instructions

Heikki Kultala, Timo Viitanen, Pekka Jaaskelainen, Janne Helkala, more

2014 IEEE Workshop on Signal Processing Systems (SiPS) > 1 - 6

2014 IEEE Workshop on Signal Processing Systems (SiPS)

Variable length encoding can considerably decrease code size in VLIW processors by decreasing the amount of bits wasted on encoding No Operation(NOP)s. A processor may have different instruction templates where different execution slots are implicitly NOPs, but all combinations of NOPs may not be supported by the instruction templates. The efficiency of the NOP encoding can be improved by the compiler...

chapter

Variable length instruction compression on Transport Triggered Architectures

Janne Helkala, Timo Viitanen, Heikki Kultala, Pekka Jaaskelainen, more

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV) > 149 - 155

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)

The SRAM memories used for embedded micro-processor devices consume a large portion of the system's power. The power dissipation of the instruction memory can be limited by using code compression methods, which may require the use of variable length instruction formats in the processor. The power-efficient design of variable length instruction fetch and decode is challenging for static multiple-issue...

chapter

Heuristics for greedy transport triggered architecture interconnect exploration

Timo Viitanen, Heikki Kultala, Pekka Jaaskelainen, Jarmo Takala

2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES) > 1 - 7

2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)

Most power dissipation in Very Large Instruction Word (VLIW) processors occurs in their large, multi-port register files. Transport Triggered Architecture (TTA) is a VLIW variant whose exposed datapath reduces the need for RF accesses and ports. However, the comparative advantage of TTAs suffers in practice from a wide instruction word and complex interconnection network (IC). We argue that these...

chapter

Inexpensive correctly rounded floating-point division and square root with input scaling

Timo Viitanen, Pekka Jaaskelainen, Jarmo Takala

SiPS 2013 Proceedings > 159 - 164

2013 IEEE Workshop on Signal Processing Systems (SiPS)

Recent embedded DSPs are incorporating IEEE-compliant floating point arithmetic to ease the development of, e.g., multiple antenna MIMO in software-defined radio. An obvious choice of FPU architecture in DSP is to include a fused multiply-add (FMA) operation, which accelerates most DSP applications. Another advantage of FMA is that it enables fast software algorithms for, e.g., division and square...

chapter

Simplified floating-point division and square root

Timo Viitanen, Pekka Jaaskelainen, Otto Esko, Jarmo Takala

2013 IEEE International Conference on Acoustics, Speech and Signal Processing > 2707 - 2711

ICASSP 2013 - 2013 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

Digital Signal Processing (DSP) algorithms on low-power embedded platforms are often implemented using fixed-point arithmetic due to expected power and area savings over floating-point computation. However, recent research shows that floating-point arithmetic can be made competitive by using a reduced-precision format instead of, e.g., IEEE standard single precision, thereby avoiding the algorithm...

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INFONA - science communication portal

Search results for: Timo Viitanen

ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA

Instruction Fetch Energy Reduction with Biased SRAMs

Variable Length Instruction Compression on Transport Triggered Architectures

Design and implementation of a multi-mode harris corner detector architecture

Hardware design methodology using lightweight dataflow and its integration with low power techniques

A 5.3 pJ/op approximate TTA VLIW tailored for machine learning

OpenCL programmable exposed datapath high performance low-power image signal processor

Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies

Low power design methodology for signal processing systems using lightweight dataflow techniques

Improved image quality in fast inpainting with omnidirectional filling

Improving Code Density with Variable Length Encoding Aware Instruction Scheduling

Rapid customization of image processors using Halide

Impact of operand sharing to the processor energy efficiency

Power optimizations for transport triggered SIMD processors

Code Density and Energy Efficiency of Exposed Datapath Architectures

Compiler optimizations for code density of variable length instructions

Variable length instruction compression on Transport Triggered Architectures

Heuristics for greedy transport triggered architecture interconnect exploration

Inexpensive correctly rounded floating-point division and square root with input scaling

Simplified floating-point division and square root

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