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In this paper, a built-in electrical test circuit is proposed to detect an open defect at an interconnect between a land on a printed circuit board and an IC. The test circuit is made of an integrating circuit, nMOS switches and a switch control circuit. A time-varying signal generated by the integrating circuit is provided to a targeted interconnect as a stimulus signal in the tests. An input buffer...
In this paper, an electrical interconnect test method and a built-in test circuit are proposed to detect and locate open defects in a 3D stacked IC made of dies, in which ESD protection circuits are not embedded. The test method is based on quiescent supply current that is made flow through the interconnect to be tested only in the tests. Feasibility of the tests is evaluated by Spice simulation....
In this paper, a built-in supply current test circuit is proposed to detect open defects occurring at interconnects between dies including an IEEE 1149.1 test circuit and locate the defective interconnects in a 3D IC. Feasibility of interconnect tests with the test circuit is examined by some experiments with a prototyping IC in which the test circuit is embedded and by Spice simulation. The simulation...
An electrical test method is proposed for detecting an open defect occurring at a data bus of a 3D SRAM IC. Targeted defects are a hard open defect and a soft one in a data bus. The test method is based on supply current of the IC. There is no need to add a circuit for the test method to an original circuit. Feasibility of the tests is examined by some experiments for a circuit made of an SRAM IC...
In this paper, a Design-for-Testability method is proposed to detect an open defect occurring at an interconnect between dies in a 3D IC. The open defect is detected by means of a supply current flowing whenever a time-varying voltage signal is provided to the targeted interconnect as a test input stimulus. Feasibility of the test method is examined by targeted experiments and circuit simulations...
We propose a testable design method of level shifters inside a liquid crystal display driver IC. The design method enables us to detect open defects in level shifters by supply current testing that are difficult to be tested by voltage testing. Also, we show by circuit simulation that more resistive open defects may be detected by supply current testing than voltage testing, if the level shifter is...
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