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A fully-compliant high-definition video decoder LSI for Blu-ray Disc (BD) player is presented. It supports MPEC-2 MP@HL, H.264 HP@L4.1, and VC-1 AP@L3 video decoding in a single chip and features resource sharing and memory management unit to achieve area/throughput efficiency. A test chip is fabricated and integrates 515 K logic gates with 522 Kbits of embedded SRAM in 90nm single-poly seven-metal...
Goals of this research are to reduce 1. Instruction address bus traffic, 2. Bus power, and 3. Latency, in instruction fetches in a computer system. We propose to move dynamic branch handler from the CPU side to the instruction memory side, and let it be able to autonomously access instructions for CPU. CPU needs only to manage the branch handler. Key to success is that the traffic between CPU and...
In this paper, we present an improvement on the normalized min-sum (NMS) decoding algorithm for low density parity check codes. The modified NMS (M-NMS) algorithm introduces a more efficient adjustment for check node update computation. Taking the sub-minimum value among extrinsic information from the variable nodes into consideration, we make the correction factor varies with different iterations...
An on-glass 6-bit R-string digital-to-analog converter (DAC) with gamma correction for panel data driver is proposed. The proposed circuit, which is composed of folded R-string circuit, segmented digital decoder, and reordering decoding circuit, has been designed and fabricated in a 3-mum low-temperature poly-Si (LTPS) technology. The area of the proposed circuit is effectively reduced to about one...
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