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The increasing demand for application specific processing on portable devices is driving the design with highly efficient hardware. Many applications are streamlined, and the delays of all streamline stages better be equalized. Unfortunately, loads at each stage of streamlined processing may vary depending on input data, making load monitoring and balancing very desirable hardware features. The aim...
In graphics processing, overlap test is a crucial step before tile-binning in tile-based rendering for embedded devices. An object in a frame is decomposed into primitives, triangles of different sizes, for processing. In tile-binning process, these triangular primitives are typically represented by bounding boxes. However, the bounding box of a primitive usually covers a significant number of tiles...
Tile-based rendering has been widely used in resource-limited graphic processing environments, e.g., for hand-held devices. Since large primitives may cover a significant number of tiles, they need to be recorded in the primitive lists of all related tiles. We propose a hierarchical primitive lists structure, which also copes with misaligned and non-square primitive problems, to minimize the primitive...
Graphics rendering requires various huge amounts of temporary data storages, prohibiting this feature from being implemented on slim embedded devices. To overcome this difficulty, we focus our effort on storage of transparent fragments after rasterization stage. We base our design on the fact that: successive frames typically will have the same or very similar number of transparent fragments located...
We propose a blocked-Z test to effectively eliminate unnecessary data traffic between triangle setup and rasterization. This method works seamlessly with the existing rendering pipeline, with or without those existing fragment-based hierarchical Z/early Z/Z tests. And it performs much better than primitive-based Z test, in terms of data structuring and coverage. In this method, primitives are blocked...
Goals of this research are to reduce 1. Instruction address bus traffic, 2. Bus power, and 3. Latency, in instruction fetches in a computer system. We propose to move dynamic branch handler from the CPU side to the instruction memory side, and let it be able to autonomously access instructions for CPU. CPU needs only to manage the branch handler. Key to success is that the traffic between CPU and...
Return stack may be popped due to branch misprediction, corrupting its contents. Meanwhile, erroneous branch history is also recorded for upcoming branch predictions. These errors are more likely in deep pipelines, and their handling affects performance seriously. We study these issues, and propose solutions with two virtues: low hardware overhead, and high branch prediction accuracy comparable with...
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