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It is known that by extracting log-likelihood ratio (LLR) values from the received MIMO signals, a MIMO detector is able to exchange a posteriori soft information with a channel decoder to improve the error performance. A minimum mean-square error with parallel interference cancellation (MMSE-PIC) detector is considered to be a practical MIMO detector, but the computational complexity for the LLR...
This paper presents a high-throughput, area-efficient and energy-efficient iterative detection and decoding (IDD) receiver for low-density parity-check (LDPC)-coded multiple-input multiple-output (MIMO) systems. A layered non-resetting IDD technique is used to minimize the number of inner iterations for a required error performance. An area-efficient minimum mean-square error with parallel interference...
A low-density parity-check (LDPC)-coded multiple-input multiple-output (MIMO) systems with iterative detection and decoding (IDD) chip is integrated in 1.33mm2 in 40nm CMOS. The maximum gross throughput is 794Mb/s for a 4×4 16-QAM configuration at 288MHz. The chip dissipates 135mW at 0.9V, achieving an energy efficiency of 170pJ/bit. Compared to non-IDD receivers, composed of state-of-the art MIMO...
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