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Approximate computing is an emerging paradigm to improve the efficiency of computing systems by leveraging the intrinsic resilience of applications to their computations being executed in an approximate manner. Prior efforts on approximate hardware design have largely focused on circuit-level techniques. We propose a new approach, clock overgating, for the design of approximate circuits at the Register...
A digital phase locked loop (DPLL) has been developed in which the phase detection is performed by a bangbang phase detector (BBPD). By dithering the offset of the BBPD, its phase detection gain can be made to be constant and independent of the reference clock jitter. Therefore the bandwidth of the DPLL can be kept constant regardless of the magnitude of the reference clock jitter. The DPLL with the...
This paper presents a direct conversion Korean standard T-DMB SoC tuner using a 65nm low power CMOS technology with the best feature of size, power and BoM ever reported. A digital F/E enhanced function is implemented to reduce analog signal processing empowered by oversampled A/D converter, digital channel selection filter and lots of digital calibration blocks. And the designed LNA excludes all...
The deterministic jitter due to the intersymbol interference (ISI) is measured on-chip by fractional oversampling, which can be used to adapt the equalization coefficients of a continuous-time linear equalizer. The effective resolution of the jitter measurement is improved to 0.1 unit interval (UI) by sampling the data input by multiphase sampling clocks spaced by 0.7 UI with the proposed fractional...
In this paper, a 65nm 1.2V 7-bit 1GSPS A/D converter with a self-calibration technique is proposed. The A/D converter is based on a folding-interpolation structure whose folding rate is 2, interpolation rate is 8. An offset self-calibration circuit with a feedback loop and a recursive digital code inspection is described. The offset self-calibration circuit reduces the variation of the offset voltage,...
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