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An 11b 60MS/s 2-channel two-step SAR ADC in 65nm CMOS is presented. The scheme shares the op-amp between channels for the residual generation and takes advantage of time interleaving for reusing the input S&H of the first stage. A reduction of the gain in the residual generator and sub-threshold operation enables the use of a power-effective, singlestage op-amp with 69dB-gain. The ADC achieves...
This paper describes a novel offset calibration technique of the residue amplifier (RAMP) for pipelined ADCs. The calibration operates in two phases, completely in the background, without requiring any interruption in the operation of the ADC. In the analog coarse correction phase most of the offset is compensated through the injection of a DC signal at RAMP's input. The digital fine correction phase...
Comparator based switched capacitor technique is a new topic because of its suitability of scaling and its inherent low power consumption. Since CBSC technique suffers from the overshoot due to the comparator delay, this paper gives a detailed analysis on the overshoot signal, and a common mode feedforward circuit is proposed to correct the overshoot error. A 10-bit 100 MS/s pseudo differential pipelined...
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