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Alessandro.DAmato@ti.comThis paper describes a second-order 3-bit incremental converter, which employs a novel Smart-DEM algorithm to compensate for the mismatch among unity elements of the multi-level digital-to-analog converter. The design, which is fabricated in a mixed 0.18–0.5 $$\upmu$$ μ m CMOS technology, achieves 16.7-bit resolution over a 5-kHz bandwidth by using 256 clock periods...