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VLSI devices are constrained by CFdd2/2 power dissipation. Low power dissipation requires low Vdd, yet reducing Vdd increases Ioff. Tunnel FETs (TFETs) have steep subthreshold swings (S.S.) and can operate at low Vdd, yet their Ion is limited by low tunneling probability. This low Ion results in large CVdd/I delay and slow logic operation. For greatly increased Ion, we had proposed a triple-heterojunction...
We report the design and simulated performance of a GaAsSb/GaSb/InAs/InP n-type triple heterojunction (3-HJ) tunnel field-effect transistor (TFET). GaAsSb/GaSb source and InAs/InP channel HJs both increase the field imposed upon the tunnel junctions and introduce two resonant bound states. The tunneling probability, and hence the transistor on-current, are thereby greatly increased. The devices were...
Transistor designs based on using mixed -L valleys for electron transport are proposed to overcome the density of states bottleneck while maintaining high injection velocities. Using a self-consistent top-of-the-barrier transport model, improved current density over Si is demonstrated in GaAs/AlAsSb, GaSb/AlAsSb, and Ge-on-insulator-based single-gate thin-body n-channel metal–oxide–semiconductor...
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