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InP Bi-CMOS technology capable of wafer-scale device-level heterogeneous integration (HI) of InP HBTs and CMOS has been developed. With this technology, full simultaneous utilization of III-V device speed and CMOS circuit complexity is possible. Simple ICs and test structures have been fabricated, showing no significant CMOS or HBT degradation and high heterogeneous interconnect yield. The heterogeneously...
Tin film about one micron thick was electroplated over a silicon wafer pre-coated with a layer of Cr and another layer of Ni by evaporation. A special sample holder was designed to apply compressive stresses in the electroplated tin film. After incubation in a vacuum oven at 160degC for 7 days, huge hillocks about 10-30 mum diameter and 30-150 mum length grew with a density about 7 per square mm....
We have developed a process for the re-growth of InP-DHBTs on selectively implanted subcollectors for the purpose of reducing the base-collector capacitance. Si+ sub-collector implants were performed at >200degC to minimize damage, an important criterion for achieving smooth morphologies in the re-grown devices. Spectroscopic ellipsometry was used to gauge the amount of implant-induced damage in...
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