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We present design strategies of high-voltage tolerant I/O circuits for interfaces of 3.3 V or higher. The test vehicle is a USB 2.0-compliant I/O circuit. This is a challenging example because USB 2.0 requires substantial over-voltage tolerance from -IV to 5.25 V. In addition, USB 2.0 requires continuous monitoring of this condition and protection when no power is present. The proposed concept is...
A phase-corrected bootstrap circuit for active capacitance compensation of a low-C ESD-protection element is discussed. A broadband 2kV-ESD-protected 10GHz amplifier fabricated in a 90nm CMOS process serves as a test vehicle. Inductive peaking compensates for the intrinsic phase shift of the multi-stage bootstrap circuit.
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