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Research-oriented simulators require flexibility and configurability in addition to good performance and reasonably accurate timing models. The M5 simulator addresses these needs by developing abstractions that promote modularity and configurability without sacrificing performance. This design allows M5 to provide a combination of capabilities–-including multisystem simulation, full-system simulation,...
Research-oriented simulators require flexibility and configurability in addition to good performance and reasonably accurate timing models. The M5 simulator addresses these needs by developing abstractions that promote modularity and configurability without sacrificing performance. This design allows M5 to provide a combination of capabilities–-including multisystem simulation, full-system simulation,...
The latency, bandwidth, and power consumption of on-chip interconnection networks are central concerns in the design of multi- and many-core microprocessors. When the global network-on-chip (NoC) is electrical, the power consumption and the limited connectivity caused by difficulties associated with global wires will limit network performance due to power or topology constraints unless applications...
Networking consumes up to 33 percent of modern data center power. Network switches are the key source of inefficiency: a switch traversal costs an order of magnitude more than a link traversal. The authors propose a new high-radix switch architecture that uses emerging integrated optical interconnect technology to reduce switch power. They tailor every component of a switch to best exploit optical...
For large-scale networks, high-radix switches reduce hop and switch count, which decreases latency and power. The ITRS projections for signal-pin count and per-pin bandwidth are nearly flat over the next decade, so increased radix in electronic switches will come at the cost of less per-port bandwidth. Silicon nanophotonic technology provides a long-term solution to this problem. We first compare...
In the push to achieve exascale performance, systems will grow to over 100,000 sockets, as growing cores-per-socket and improved single-core performance provide only part of the speedup needed. These systems will need affordable interconnect structures that scale to this level. To meet the need, we consider an extension of the hypercube and flattened butterfly topologies, the HyperX, and give an adaptive...
Data centers and HPC clusters often incorporate specialized networking fabrics to satisfy system requirements. However, Ethernet's low cost and high performance are causing a shift from specialized fabrics toward standard Ethernet. Although Ethernet's low-level performance approaches that of specialized fabrics, the features that these fabrics provide such as reliable in-order delivery and flow control...
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