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In this paper, retention characteristics of the trap-assisted tunneling (TAT) mechanism are investigated in sub 20-nm NAND flash memory. Total charge loss source for the TAT mechanism ($ {\Delta V_{\rm th({\mathrm{ TAT}})}}$ ) becomes larger with baking temperature, while the source for the detrapping mechanism is almost constant. This temperature dependence of the TAT mechanism becomes larger as...
We measured RTN characteristics in NAND flash cell array and test structure having 27 nm design rule depending on different program and erase states. From these measured results, we analyzed the trap properties along the active width direction from of NAND flash cell. Using special analysis methods, we verified the validity of this characterization tool and applied it to various processed NAND flash...
Multi level RTNs have been measured in GIDL current of DRAM cell transistor. Three-level RTN which has not been reported in GIDL current was observed. We found that this RTN has unique characteristics which could be distinguished from two-level RTN by single trap and four-level RTN due to two traps. Also, we discussed bias dependency of time constants of the three-level RTN.
An analytic expression was obtained to examine the dependence of dielectric layers thickness and silicon radius on Vth shift, which is an important characteristic of gate all around SONOS/TANOS memory. As the radius of silicon decreases, the Vth shift decreases because of increasing capacitance in dielectric layers under the condition of same trapped charge density. The Vth shift is almost linearly...
Recently the cell integration density of NAND flash memory is increasing rapidly due to its simple structure suitable for high resolution lithography. Therefore, the reduction of cell size has been the most important issue. However, with the increase in the number of the cells and the scale-down of the cell size, the NAND cell string has some problems such as small on-cell current and poor program/erase...
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