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Nowadays, the stereoscopic 3D (S3D) has become more and more popular. However, sometimes people can still feel uncomfort when watching S3D videos. This phenomenon, to some extent, comes from the non-synchronization of the left and right views. That is, when a S3D videos is shot by two individual cameras, the left frames can't match exactly with their corresponding right frames in time domain. If the...
In this paper, the authors present an event-driven system with resources to run applications with different degrees of complexity in an energy-aware way. The architecture uses effective system partitioning to enable duty cycling, SIMD instructions, power gating, voltage scaling, multiclock domains, multivoltage domains, and extensive clock gating. The system has sufficient computational power to run...
Ultra low voltage operation promises to reduce power dissipation for wireless sensor network applications. Such ultra low voltage systems are likely to have many sub-systems operating at different frequencies and VDDs from super-threshold to sub-threshold. Synchronizers are needed to interface among these domains. However, VDD scaling rapidly degrades synchronizers performance making them unsuitable...
This paper addresses problems of chaos control and synchronization of a new four-dimensional (4D) chaotic system by applying the passive theory. With the study of the property of a passive system, the sufficient conditions were derived under which the controlled and error systems of the 4D chaotic system could be equivalent to passive systems. It can be proved that the new systems transformed by the...
Two adaptation schemes based on on-chip measurement of failure rates have been proposed to reduce the effects of process, voltage, temperature and data rate variations on synchronizers on chip. One scheme is to select the best synchronizer out of a number to improve the synchronizer performance subject to process variation on chip. Compared to increasing the transistor size, this scheme can further...
We describe a new latch circuit designed to give a high performance in low voltage synchronizer applications. By increasing the latch current only during metastability, we can more than maintain the value of the metastability time constant, tau without significantly increasing the power. Our circuit also reduces the variation of tau with Vdd and temperature, so that it has a lower tau at 50% Vdd than...
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