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A 1080 p high profile H.264 encoder is designed by the robust reusable silicon IP methodology and fabricated in a 0.13 mum CMOS technology with an area of 10 mm2 and 242 mW at 145 MHz. Compared to the state-of-the-art design targeted at 720 p baseline, this design reduces 53.4% power and 46.7% area through parallelism enhanced throughput and cross stage sharing pipeline.
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