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An oxide/silicon core/shell nanowire (OSCSNW) MOSFET is proposed. Its fabrication process and performance are described in detail. The ION/IOFF ratio of the OSCSNW is improved by more than one order of magnitude compared with traditional nanowire (TNW) devices. Excellent scaling characteristics are also observed from the OSCSNW MOSFETs with minimal threshold voltage roll-off, drain induced barrier...
FinFET device, the promise one of all candidates which may extend CMOS scaling to 10nm and beyond, has attracted intensive research interest in recent years. In paralleling the process technology and circuit design methodology, a compact model which serves as a link between the process technology and circuit design is strongly demanded. In this paper, we first review the FinFET process technology...
A drain current model with improved computational efficiency for double-gate (DG) MOSFETs is presented in this paper. Based on our previously proposed potential model, the drain current model is obtained with the implementation of an improved calculation method and the computation efficiency is substantially enhanced. 2-D device simulation (TCAD) is extended to verify the proposed model. In addition,...
A unified drain current model for undoped or lightly doped double-gate (DG) and surrounding-gate (SRG) MOSFETs incorporating velocity saturation effect are presented in this paper. The unified charge-based core model for undoped or lightly doped DG and SRG MOSFETs is presented first. Caughey-Thomas engineering mobility model with exponent factor n=2 is then integrated self-consistently into the unified...
A generic DG MOSFET analytic model with vertical electric field induced mobility degradation effects is proposed and verified in this paper. It is shown that the proposed model is valid for different operation modes including symmetric DG (sDG), asymmetric DG (aDG) and independent DG (iDG). Extensive two-dimensional (2-D) device simulation is performed to verify the proposed model.
ULTRA-SOI is a new generation of the channel-potential-based non-charge-sheet model for the dynamic depletion (DD) Silicon-On-Insulator (SOI) MOSFET, developed by TSRC group in EECS department of Peking University with many year efforts. The model is formulated with a fully physical derivation from the Poisson's equation to solve the potential along the vertical direction of the silicon film. The...
Based on the non-equilibrium Greenpsilas function simulation, the analog/RF performance of Coaxial Carbon Nanotube Field Effect Transistor (CNTFET) including the trans-conductance efficiency gm/Id, cutoff frequency ft, and maximum oscillation frequency fmax are analyzed in details. The analysis method is described and the CNTFET analog/RF performance dependence on the operation bias, device chirality,...
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