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In this work, the benefits of memristor‐based multilevel memories are described along with their design problems. Starting with measurements of discrete actual devices, a discrete memristor‐based multilevel memory is developed. It uses a printed circuit board in order to connect eight packaged memristors from Bio Inspired to test a ternary arithmetic logic unit on a field programmable gate array....
High-Performance Analog-to-Digital Converter (ADC) have high requirements concerning sampling rate and linearity. Therefore a new formula is derived to determine, which pipeline stage dependent on the used capacitor sizes needs to be calibrated for the targeted linearity. Furthermore, a model of a 16 bit and 200 MS/s pipeline ADC is described. A combination of a digital foreground and a digital background...
This paper presents a novel dual-band class-E/F power amplifier (PA) with switchable output power. It is targeted to work in a BPSK/OOK transmitter in smart facility applications like an autarkic asset-tracking system based on small sensor nodes. The amplifier is fully-integrated and able to operate at both 434 MHz and 868 MHz without the need for additional inductors, making the design very area-efficient...
Flat-Panel C-arm Computed Tomography (CT) suffers from pixel saturation due to the detector's limited dynamic range. We describe a novel approach of analog, non-linear tone mapping (TM) for preventing detector saturation. An analog TM operator (TMO) applies a non-linear transformation in a CMOS (complementary metal-oxide semiconductor) sensor and its inverse TMO based on 14-bit digital raw data. This...
This paper presents a diversity integrated circuit (IC) for digital satellite radio (SDARS) at 2.3GHz. The IC contains an RF circuit which enables fast adaptive processing of up to three antenna signals for maximum ratio combining in a fast fading scenario. The RF front-end of the diversity system is integrated using 150nm CMOS technology. The phase of each of the three input paths can be adjusted...
In this paper, a transmitter for outdoor positioning application such as animal tracking is introduced. Class-E power amplifiers are exploited in the transmitter system in order to increase the energy efficiency for the demand of long operation duration of the system. Along with the need of power saving, a circuit topology is proposed to realize the modulation based on Binary Offset Carrier (BOC)...
Pipeline Analog to Digital Converters (ADC) use a sub-ADC in each pipeline stage. They require a much higher sampling rate and less accuracy. For that reason Flash ADCs are predestined for sub-ADCs. In this paper a differential Flash ADC is presented for a targeted pipeline ADC with 16 Bit, 200 MS/s and a 1.5 Bit resolution per stage. The overall accuracy of the Flash ADC is 30mV and a typical propagation...
This work describes new methods of handling ex-ceedings of the supply range in analog computation stages. These are handled as pseudo-digital and analog carry signals and used to regulate the gain of the stage where they occur as well as all computation stages that follow. A complete example for such an analog computation is simulated and presented and critical parts of the architectures are addressed...
This paper discusses different approaches to improve the settling behavior of phase lock loops (PLL). Starting with a state-of-the-art PLL, a structure with an additional dynamic changing Loop-Filter and another structure with feed forward control are proposed. The main topic of this paper is the adaption of modern control theory in the design of PLL systems to improve reference action of the control...
This paper presents a new reference system with emphasis on low power design and high power supply rejection. The untrimmed reference provides a 600 mV output voltage, which only differs by 5.75mV in the temperature range between −40°C and +125°C and a PSRR of −157.2dB at 10Hz. The core part of the reference produces a reference potential of 416.1mV with a deviation of only 1.59 mV. Moreover, the...
This paper contains the development and verification of low noise amplifier stages (LNA) within the framework of a front-end for digital satellite radio diversity receiver operating around 2.3 GHz. First, a low noise high gain LNA is developed to reach the high requirements of satellite radio reception. Therefore a single-ended cascode architecture is chosen. The simulated noise figure is 0.58 dB...
This paper presents and analyses a phase shifter for diversity receivers, which modulates the I-/Q-vector in the constellation diagram. The system consists of a three stage programmable gain amplifier (PGA) chain in both branches. The design covers the full phase range of 360°. Each stage can be programmed to amplify the incoming signal between 19 dB and 63 dB with a centre frequency of 3 MHz. The...
This paper describes the design and verification of phase lock loop (PLL) components within the framework of a front-end for digital satellite radio diversity reception. First, the functionality of the implemented PLL is described by a block diagram. Second, individual PLL components are presented and analysed. Altogether a voltage controlled oscillator (VCO), an automatic amplitude control (AAC),...
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