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We have designed pass-transistor logic (PTL)-based D flip-flop and T flip-flop to be used in finite field multiplication. Since both CMOS and PTL have their respective advantages in area, speed, and power, we have compared two different designs (conventional implementation and improved implementation) of serial-parallel finite field multiplication using pure CMOS, pure PTL, and hybrid PTL/CMOS logic...
This paper presents a cell-based AISC design flow where the traditional CMOS cell library is replaced by pass-transistor logic (PTL) cell library. In particular, we develop an automatic PTL logic synthesizer to perform area-oriented synthesis by exploiting the characteristics of the PTL cell circuits. Two methods are used to reduce the area cost. The first method, called buffer elimination, for the...
In the past two decades, pass transistor logic has been shown to have smaller power and area cost compared to traditional CMOS logic for some applications. Some important issues related to the design of pass transistor cell library are discussed in this paper. First, the transistor sizing for the special inverter circuit in the cell library is addressed, which is quite different from the sizing of...
In this paper, the simplified DSP implementation of training sequence-based on Least Square (LS) channel estimation in MIMO-OFDM system was demonstrated. A proper design of the training sequence not only simplifies channel estimation, but also still obtains the best estimation performance. For the purpose of getting channel estimation algorithm to work in real time, some main approaches are carried...
An efficient logic synthesis based on pass-transistor logic (PTL) is developed which can generate both combinational and sequential circuits. Instead of using traditional CMOS cell library which usually contains hundred of different types of cells, the proposed PTL synthesizer uses only three types of cells: 2-to-1 multiplexer (MUX), inverter, and D flip-flop (DFF). The PTL synthesizer first employs...
Memory has become one of the critical components in many applications. This paper presents new designs of SRAM memory circuit and architectures for applications in 3D graphics, JPEG2000, and multimedia codec. In the 3D graphics pipeline, the memory initialization is realized by modifying the circuits in the SRAM decoder and storage cell. In the bit-plane coder (BPC) of JPEG2000, we propose a new 3D...
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