The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, we introduce a systematic power analysis framework for SoC designs using bottom-up power modeling integrated with top-down power estimation. Four power analysis tools have been realized: (1) PowerBrick, a power characterization tool to construct power libraries for standard cell library and memory compiler, (2) PowerMixer, an RTL/gate-level power estimator for large logic design, (3)...
SRAM has been under its renovation stage recently, aiming to withstand the ever-increasing process variation as well as to support ultra-low-power applications using even subthreshold supply voltages. We present in this paper a novel P-P-N-based 10T SRAM cell, in which the latch is formed essentially by a cross-coupled P-P-N inverter pair. This type of cell can operate at a voltage as low as 285 mV...
In this paper we present a generic network security processor (NSP) design suitable for a wide range of security related protocols in wired or wireless network applications. Following the platform-based design methodology, we develop four specific platforms, i.e., architecture platform, EDA platform, design-for-testability (DFT) platform, and prototyping platform, for our NSP design. With these platforms,...
This paper presents a low-power SRAM design with quiet-bitline architecture by incorporating two major techniques. Firstly, we use a one-side driving scheme for the write operation to prevent the excessive full-swing charging on the bitlines. Secondly, we use a precharge-free pulling scheme for the read operation so as to keep all bitlines at low voltages at all times. SPICE simulation on a 2K-bit...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.