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In this work, we investigate the impact of varying silicon-body thickness, Tsi i.e 5 nm, 7 nm, 10 nm and 12 nm on the digital figures-of-merit performance of Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs of 10 nm gate length with different ground plane (GP) structures under the double-gate (DG) operation-mode. We show that degradations of the digital characteristics i.e DIBL, subthreshold-slope...
In this work, we investigate the impact of using different gate dielectric materials i.e HfO2 and Si3N4 as compared to the conventional SiO2 with equivalent oxide thickness (EOT) of 1.2 nm on the digital and analog performance of UTBB SOI MOSFETs of 10 nm gate length with different ground plane (GP) structures under the double-gate (DG) operation-mode by numerical simulations. It is found that Si3N4...
In this work, we study the effect of the drain voltage on the threshold voltage extraction in long-channel MOSFETs by the transconductance and transconductance-to-current-ratio change methods, using analytical modeling and experimental data obtained on UTB SOI MOSFETs.
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