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This paper presents a SAR ADC using passive noise shaping and noise quantizer techniques. A ping-pong residue switching enables noise shaping at high sampling rate. The prototype in 14 nm achieves 69-dB SNDR at 25-MHz BW and 300 MS/s. The FOMs and FOMw are 169 dB and 20.5 fJ/conv.-step, respectively. With noise shaping only, the SNDR is 66.2 dB at 33-MHz BW and 400 MS/s.
This paper presents a 4-way 1.6-GS/s time-interleaved (TI) SAR ADC with fast reference charge neutralization (CN) and background timing-skew calibration. The SAR sub-ADC uses a flip-flop-less digital control unit to achieve 400MS/s operation. The prototype in 16-nm CMOS occupies an active area of 0.023 mm2. From a 0.95-V supply, the power consumption is 8.2 mW at 1.6 GS/s. The peak SNDR is 55 dB and...
This brief presents a new circuit architecture for linear-in-decibel, constant-bandwidth variable gain amplifier (VGA). To obtain high linearity under low-voltage operation, this VGA is a closed-loop structure. In loop amplifier design, two techniques are applied: first, the loop amplifier is given finite input impedance. This arrangement keeps the VGA bandwidth constant under different gain setting...
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