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Approximate computing introduces a new era of low-power and high-speed circuit designs. Instead of strict accurate computation, relaxed requirements might increase performance and reduce power consumption with a simplified or inaccurate circuit. One of the recent remarkable research efforts is the accuracy-configurable approximate adder designs, which can gracefully operate in both approximate (inaccurate)...
Interconnect design has recently become one of the important factors that affect the circuit delay and performance especially in the deep submicron technology. The modelling of interconnects is typically based on using Elmore definitions of the delay time and rise time. So, a general formula for Elmore delay time and rise time in the fractional order domain are presented in this work. It is found...
The paper proposes a method to synthesize a digital controller for multiphase switched capacitor converters (SCCs). A specific requirement to the controller is that, regardless of external conditions, it should provide pulses of fixed frequency and width. Asynchronous (self-timed) digital circuits fulfil this requirement by definition. However, their design can be quite complex, especially if an SCC...
Computing circuits suffer from the process, voltage and temperature variations and aging. These factors reduce yield and lifetime of the circuits and therefore limit the advance in modern computing technology. The process variations and aging result in timing failures that often can be resolved by delay matching. However, this strategy requires delay elements which cause additional power cost. We...
Asynchronous logic and power gating are promising techniques for low duty cycle applications which need maximal energy efficiency, which are becoming more common-place with the popularity of wireless and embedded systems. This paper investigates the potential use of Nano/Micro- Electro- Mechanical (N/MEM) switches as the means of power gating asynchronous computation. A systematic optimization of...
We propose a new design of an asynchronous speed-independent SRAM controller that is tolerant to variations in supply voltage and can trade off performance for power consumption. It uses the standard 6T memory cells and is more robust than a comparable speed-independent design in literature due to a delay-insensitive interface to bit-lines. Designing an asynchronous SRAM controller presents a fascinating...
The paper introduces a new reusable asynchronous component, called WAITX element, that arbitrates between two requests. In contrast to the traditional mutex, the requests are not required to be persistent, i.e. can be withdrawn at any moment, have hazards or even have high-frequency bursts, e.g. they can be outputs of voltage comparators. It is guaranteed that (i) hazards will never propagate past...
Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant applications. It can offer substantial reductions in circuit complexity, delay and energy consumption by relaxing accuracy requirements. In this paper, we propose a novel energy-efficient approximate multiplier design using a significance-driven logic compression (SDLC) approach. Fundamental to this approach...
This paper describes an energy efficient boot-strapped CMOS inverter for ultra-low power applications. The proposed design is achieved by internally boosting the gate voltage of the transistors (via the charge pumping technique), and the operating region is shifted from the sub-threshold to a higher region, enhancing performance and improving tolerance to PVT variations. Despite the proposed bootstrapped...
Delay path reconfiguration is used to control frequency output in Digitally Controlled Oscillators. In order to achieve a very low frequency range, if the delay path is not properly designed, this would result in large area overhead and leakage power loss. An alternative delay path is proposed for the DCO, based on a unit delay as the smallest possible delay, with added architecture to multiply the...
Capacitance sensors are widely used for sensing physical parameters. Conventional capacitance to digital methods use complex analog ADC techniques which are power hungry. Recently a fully digital solution was proposed with improved power consumption. This paper describes a number of problems in that solution, analyzes these problems, and proposes a new design free of these problems. A voltage senor...
Oscillators are needed in many systems for time keeping purposes. They are often called timers. In low duty cycle systems, such as wireless sensors, such oscillators may incur a significant portion of system power consumption. Extensive research exists in making on-chip oscillators low power. However, the other part of the time keeping function, that of computing the number of oscillation cycles,...
Power regulators and converters impose high requirements on the latency and resilience of their control circuitry. In this paper we design a speed-independent multiphase buck controller based on a novel lazy token ring architecture, that allows overlapping the charging cycles of multiple phases as well as simultaneous activation of all phases to handle the sudden power demand. The advantages over...
The paper introduces a new reusable asynchronous component, called Opportunistic Merge element, that merges two or more request-acknowledgement channels into one and is allowed to opportunistically bundle requests from different input channels if they arrive sufficiently close to each other. We present a speed-independent implementation of this component and verify some of its correctness properties...
Nano-Electro-Mechanical (NEM) relay is a promising device overcoming the energy-efficiency limitations of CMOS transistors operating at or near the sub-threshold voltage. Many exploratory research projects are currently under way investigating the mechanical, electrical and logical characteristics of NEM relays. One particular issue that this paper addresses is the need for a scalable and accurate...
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