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This work investigates the stability and AC performance of standard tied-gate 6T and several novel sub-threshold FinFET SRAM cells using independent-gate control technique. Significant nominal READ Static Noise Margin (RSNM) improvements are observed in these novel cells with the tolerable degradation of “cell” READ access time. However, Write-ability deteriorates and becomes a serious concern for...
This paper investigates the Static Noise Margin (SNM) of FinFET SRAM cells operating in sub-threshold region using analytical solution of 3D Poisson's equation. An analytical SNM model for sub-threshold FinFET SRAM is demonstrated and validated by TCAD mixed-mode simulations. The stabilities of several novel independently controlled-gate FinFET SRAM cells are examined. Significant nominal RSNM improvements...
This paper presents a detailed analysis on the impacts of various gate-oxide breakdown (BD) paths in column-based header- and footer-gated SRAMs. It is shown that with gate-oxide BD, the RSNM (read static noise margin) degrades, while the WM (write margin) improves in general. The effects of gate-to-source BD of cell transistors are shown to confine to the individual cell, while multiple cells suffering...
This paper investigates the Static Noise Margin (SNM) of Ultra-Thin-Body (UTB) SOI SRAM cells operating in subthreshold region using analytical solution of Poisson's equation validated with TCAD simulations. An analytical SNM model for UTB SOI SRAM cells operating in subthreshold region is presented. Our results indicate that back-gate bias (Vbg) can mitigate the Read SNM (RSNM) variability of UTB...
The proposed selective-back gate bias technique using dual BOX improves SRAM stability, reduce leakage power, and enhances sub-array access speed while preserving overall area efficiency. TCAD simulations show that nominal Read SNM is improved by 37%, and the cell is very immune to process variations such as RDF, TSi, and TBOX. Thus, it is very suitable for high-performance on-chip cache and SOC embedded...
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