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We present a methodology to simulate industrial integer-$N$ phase-locked loops (PLLs) at a verification level, as accurate as and faster than transistor-level simulation. The accuracy is measured on the PLL factors of interest, i.e., locking time, power consumption, phase noise and jitter (period and long-term). The speedup factor tends to the division ratio $N$ for device-noise simulations. We...
We present a method to speed up noise-free and noisy time domain simulations of industrial integer-N PLLs, while extracting the main factors of interest which circuit designers are interested in, i.e., locking time, power consumption, phase noise and jitter, within desirable error levels. The procedure is based on oscillator's sensitivity analysis and on the creation of a phase macromodel for it and...
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