The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Most digital content nowadays is protected by a digital rights management (DRM) framework to prevent piracy. Since much content is distributed throughout the world, modern DRM frameworks must protect the confidentiality and integrity of the data, even from rootkits or physical tampering. Secure processors have been proposed to ensure secure executions by performing memory encryption and integrity...
The capacity of cache memory has reached the megabytes magnitude and various smart cache algorithms have been introduced. However, cache systems still suffer from plenty of cache misses, especially for memory-intensive applications. In this paper, we reveal that a vast majority of the remaining cache misses on LLC are caused by long interval, unpredictable re-reference accesses. Based on the analysis,...
The data volume used in online analytical processing (OLAP) applications is rapidly increasing because of the increasing popularity of various Web services and emerging sensor technologies. Since the amount of accumulated data is frequently too large to store in an in-memory database, it is necessary to have a secondary storage to store such big data. On the basis of this premise, the most important...
Computation beside a data source plays an important role in achieving a high performance with low energy consumption in Big Data processing. In contrast to that of a conventional workload, the processing of Big Data frequently requires that a massive amount of data in distributed storage be scanned. A key technique for reducing energy-consuming processor loads is to install a reconfigurable accelerator...
Cloud computing has rapid growth in enterprise and academic areas. Computing platform makes up the transition from physical servers to virtual machines (VMs) in the cloud. Instead of many advantages, VMs remain several problems to employ effective utilization of physical computing resources, especially many-core accelerators. Even though GPGPU is a hopeful solution for high-load applications, existing...
This paper presents an efficient and scalable implementation of an FPGA-based accelerator for sliding-window aggregates over disordered data streams. With an increasing number of overlapping sliding-windows, the window aggregates have a serious scalability issue, especially when it comes to implementing them in parallel processing hardware (e.g., FPGAs). To address the issue, we propose a resource-efficient,...
This paper shows the design and evaluation of an FPGA-based accelerator for sliding-window aggregation over data streams with out-of-order data arrival. We propose an order-agnostic hardware implementation technique for windowing operators based on a one-pass query evaluation strategy called Window-ID, which is originally proposed for software implementation. The proposed implementation succeeds to...
Detailed mechanism of optical illusion caused by visual neurons in human brain has not been well understood, and its numerical simulation is helpful to analyze visual system of humans. This paper describes implementation techniques of parallel numerical simulation to help understanding optical illusion by using a GPU-accelerated PC cluster. Our parallel acceleration techniques include following three...
As the number of cores as well as the network size in a processor chip increases, the performance of each core is more critical for the improvement of the total chip performance. However, to improve the total chip performance, the performance per power or per unit area must be improved, making it difficult to adopt a conventional approach of super scalar extension. In this paper, we explore a new...
As the number of core integration on a single diegrows, buffers consume significant energy, and occupy chip area. A bufferless deflection routing that eliminates router's inputportbuffers can considerably help saving energy and chip areawhile providing similar performance of existing buffered routing, especially for low-to-medium network loads. However when congestion increases, the bufferless frequently...
Numerical simulation for visual processing of the human brain is one of time-consuming applications. This paper shows acceleration techniques for a simulation program of the visual processing. We parallelize convolution calculations, which are core operations, which the simulation program requests, on a GPU-accelerated PC cluster. Our implementation includes three improvement points. Firstly, we consider...
One of the significant issues of processor architecture is to overcome memory latency. Prefetching can greatly improve cache performance, however, it has the drawback of cache pollution unless its aggressiveness is properly set. Although several techniques for prefetcher throttling have been proposed which use accuracy as a metric, their robustness were not sufficient due to the variations between...
In this paper, a runtime system termed CODIE is proposed to execute sequential part of programs efficiently in a many-core architecture. All independent processing elements in a many-core architecture use a shared network and off-chip memory. Therefore, contentions on such resources substantially degrade the system performance. On the CODIE system, when a cache miss occurs, the system first initiates...
The role of network-on-chip (NoC) is becomingmore important as the number of processing elements (PE)integration onto a single chip increases. Lowering powerconsumption while providing capability of high-performancecommunication is a challenging problem for the design offuture NoCs. In this paper we propose OREX, which is a hybridNoC consisting of an optical ring and an electrical crossbarcentral...
Vulnerabilities such as buffer overflows exist in some programs, and such vulnerabilities are susceptible to address injection attacks. The input data tracking method, which was proposed before, prevents I-data, which are the data derived from the input data, being used as addresses. However, the rules to determine address injection attacks are vague, which produces many false-positives and false-negatives...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.