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Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shipped to the customers fault-free. However, at-speed tests have been known to create higher-than-average switching activity, which normally is not accounted for in the design of the power supply network. This potentially creates...
ESD reliability of MOS gate dielectrics and of input circuitry is investigated for a 90 nm CMOS technology. Performance degradation is observed at voltages lower than the breakdown voltage. It is found that the input transistor gate dielectric breakdown voltage depends strongly on the source-body voltage and, consequently, on the input circuit design.
ESD-induced latent damage in CMOS integrated circuits has been thoroughly investigated after cumulative low-level ESD stress. A study of the latent damage for transistors at the package level has been performed with various kinds of ESD stress modes. The impact of latent damage on circuit performance degradation was also evaluated using a 64 Mb DRAM chip as a DUT.
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