The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
An evaluation of electrostatic-discharge (ESD) reliability by changing the source-end layout of 45-V HV pLDMOS devices is investigated in this paper. After testing and systematic analysis, it can be found that a traditional pLDMOS sample is always very weak in ESD issues (It2= 0.107-A). At the same time, if a pLDMOS with a stripe type embedded SCR (p-n-p-arrangement in the drain-end); the corresponding...
For the anti-ESD reliability consideration, the drain-side with super-junction structures and “npn” embedded type SCRs of nLDMOS transistors are investigated in this paper. From the experimental data, we can find that the layout manner of super-junction types in the drain-side have positive impacts on the anti-ESD capability. On the other hand, as the drain-side added another item i.e. an embedded...
Repercussions on the reliability capability and electrical performance of power p-channel LDMOS devices by different discrete-distributed architectures in the drainside are investigated in this paper. Here, in order to effectively improve the reliability issues, a drain-side "NPN" and "PNP" styles of pLDMOS-SCR with some discrete-distributed areas arrangement are fabricated by...
In order to effectively improve the ESD capability of a p-channel lateral-diffused MOS device, we aimed at the anti-ESD protection capability of the different layout types in the drain-side for the 0.25-μm 60-V high voltage p-channel LDMOS devices. Here, a drain-side pnp arranged-type in a pLDMOS-SCR parasitic structure is used to investigate the layout placement effect. At first, the layout type...
The impact of layout-type dependences on anti-ESD robustness in a 0.25 μm 60 V process will be investigated in this paper, which included the traditional striped-type nLDMOS, waffle-type nLDMOS, and nLDMOS embedded with a pnp-manner SCR devices. Then, these nLDMOS devices are used to evaluate the influence of layout architecture on trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown...
How to effectively enhance the reliability robustness in high-voltage BCD processes is an important issue. A p-channel lateral-diffused MOSFET with an embedded SCR which is formed by implanting N+ doses in the drain side and divided into five regions, this structure called as the "pnpnp" arranged-type of pLDMOS-SCR in this paper (diffusion regions of the drain side is P+-N+-P+-N+-P+). Then,...
This study reports the impacts of various drain end layouts on the reliability and electrical performance of 60-V p-channel laterally diffused metal–oxide-semiconductor (pLDMOS) FETs. For effectively improving the reliability, drain-end “N-P-N” and “P-N-P” permutated pLDMOSs embedded with silicon-controlled rectifiers (pLDMOS–SCRs) with discrete regulated structures in the drain strap were manufactured...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.