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In a convolutional neural network (CNN), convolution calculation can account for about 90% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification,...
NULL Convention Logic (NCL) is a promising design paradigm for constructing low-power robust asynchronous circuits. The conventional NCL paradigm requires pipeline registers for separating two neighboring logic blocks, and those registers can account for up to 35% of the overall power consumption of the NCL circuit. This brief presents the Register-Less NCL (RL-NCL) design paradigm, which achieves...
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