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This study presents a generalised architecture for cube operation based on Yavadunam sutra of Vedic mathematics. This algorithm converts the cube of a large magnitude number into smaller magnitude number and addition operation. The Vedic sutra for decimal numbers is extended to binary radix-2 number system considering digital platforms. The cubic architecture is synthesised and simulated using Xilinx...
Signed digit representation is vital for implementation of fast arithmetic algorithm and efficient hardware realization. Redundant binary (RB) number representation is the most widely used technique for representation of signed digit number. Again RB representation has ability to provide carry propagation free addition. In this paper we have presented an efficient modified redundant binary (MRB) adder...
For implementation of a fast arithmetic algorithm and efficient hardware realization, signed digit representation is crucial. Redundant binary (RB) and 2's complement number representation is the most widely used technique for representation signed digit number. The drawbacks of RB technique include multi valued logic as well as need of unconventional hardware blocks. Though 2's complement notation...
Software testing is one of the important stages of software development. In software development, developers always depend on testing to reveal bugs. In the maintenance stage test suite size grow because of integration of new technique. Addition of new technique force to create new test case which increase the size of test suite. In regression testing new test case may be added to the test suite during...
Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique computational technique for calculations based on 16 Sutras (Formulae). Novel Binary divider architecture for high speed VLSI application using such ancient methodology is presented in this paper. Propagation delay and dynamic power consumption of a divider circuitry were minimized significantly by removing unnecessary...
This paper presents the architecture and modeling of modular multiplication for RSA public key algorithm. It supports multiple lengths like 128 bits, 256 bits, 512 bits of data. In this paper simple shift and add algorithm is used to implement the modular multiplication. It makes the processing time faster and used comparatively smaller amount of space in the FPGA due to its reusability. Each block...
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