The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Carbon nanotubes (CNTs) due to their unique mechanical, thermal and electrical properties are being investigated as promising candidate material for on-chip and off-chip interconnects. The attractive mechanical properties of CNTs, including high Youngs modulus, resiliency and low thermal expansion coefficient offer great advantage for reliable and strong interconnects, and even more so for on-chip...
Three-dimensional Networks-on-Chip (3D NoCs) are based on Through-Silicon-Vias (TSV), which offer several advantages such as stacking, high throughput and energy efficiency. However, TSVs suffer from design process variations. On the other hand, designing purely asynchronous serializers enables reliable inter-tier communication with moderate performance overhead. A side benefit lies in the intrinsic...
In order to improve performance and reduce cost, multi-processor system on chip (MPSoC) is increasingly becoming attractive. At the same time, 3D integration emerges as a promising technology for high density integration. 3D homogeneous MPSoCs combine the benefits of both. However, high current demand and large on-chip switching activity variations introduce severe power supply noises (PSN) for 3D...
Three-dimensional (3D) integration is considered to be a promising technology to tackle the global interconnect scaling problem for tera-scale integrated circuits (ICs). 3D ICs typically employ through-silicon-vias (TSVs) to connect planar circuits vertically. Due to its immature fabrication process, several defects such as void, misalignment and dust contamination, may be introduced. These defects...
3D power delivery networks are essential for delivering supply voltage to all tiers. PDNs on each tier are mesh networks that are bridged together using Through-Silicon-Vias (TSVs) to devise 3D PDNs. However, a host of vulnerabilities influence their resiliency and reliability such as power supply noise, long parasitic current paths, switching activities, high frequencies, and sensitivity to temperature...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.