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Sub 200 nm wafer-to-wafer (w2w) overlay accuracy on the entire 300 mm wafer was successfully demonstrated via wafer level Cu/SiO2 hybrid bonding. Cu bonding pads relevant for back-side illuminated (BSI) complementary metal oxide semiconductor (CMOS) image sensor (CIS) were used for the experiment. Further, a crucial component to improve the overlay accuracy, namely the overlay model which identifies...
The use of CMOS wafers imposes important limitations for W2W (Wafer-to-Wafer) or C2W (Chip-to-Wafer) bonding: low processing temperature (max. 400°C), no mobile ions and extreme cleanliness. Additional to substrates preparation a special focus is directed on cleaning and maintaining the wafers clean during processing. Special cleaning processes were adopted for CMOS-compatible applications. The main...
Metal films can be used as bonding layers at wafer-level in manufacturing processes for device assembly as well as just for electrical integration of different components. One has to distinguish between two categories of processes: metal thermo-compression bonding on one side, and bonding with formation of a eutectic or an intermetallic alloy layer. The different process principles determine also...
To meet future 3D stacking requirements on wafer-to-wafer level, we successfully demonstrate oxide-oxide direct bonding on 200 mm with and without copper level utilizing face-to-face alignment and bonding within one process module as well as on the same chuck.
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