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We propose SRAM bitcells with asymmetric halo implant dose MOSFET (AH-MOS) by introducing additional masks for halo implant steps. AH-MOS has different drain-source currents (Ids) between forward and reverse directions (Fig. 1). By implanting high and low dose for drain and source regions respectively, Ids flowing from drain to source (forward) gets larger than that from source to drain (reverse)...
In this paper, we propose an SRAM macro that realizes 0.5V operation by combining a device technique with simple design architecture. Regarding the device technique, we utilize asymmetric halo implant MOSFETs, which enables to enhance both the static noise margin and write margin of SRAM, simultaneously. As for the design technique, dynamic body-bias scheme which operates body bias dynamically is...
This paper presents that Advanced Actively Body-bias Controlled (Advanced ABC) technology contributes to enhancing operation margins of SRAMs. Significant enhancement of Static Noise Margin (SNM) is successfully realized by using a body bias of load transistors while suppressing threshold-voltage variations for the first time. It is demonstrated that the write and read margins of 65nm-node SOI SRAMs...
In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve...
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