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To achieve a 0.5-V low-power high-speed robust bus, a dynamic bus architecture, combined with a dynamic driver and a dynamic receiver for small leakage current with stacked MOSFETs, is proposed. In particular, the dynamic driver enables high speed even at 0.5 V with increased gate-over-drive by changing the power lines from VDD/2 in the standby mode to VDD in the active mode. It further speeds up...
To achieve high-speed 0.5-V SRAMs, a dynamic power-supply 5T cell, and a multi-divided array with selectively-boosted 5T-cell power lines are proposed. Layout and post-layout simulation with a 28-nm planar-FD-SOI MOSFET reveal that a 4-kb array in a 128-kb core using the proposals operates at 350-ps cycle with x6 faster and x13 lower power than the counterpart 6T-cell array, while maintaining a small...
The goal of this research work is to explore technology and memory architectures to reduce power consumption with low area and high speed of operation. We proposed two different architectures of SRAM memory. First is focused on reducing dynamic power consumption and area, with high speed of operation. Second architecture is focused on reducing leakage power with good speed and optimized area.
To achieve 0.5-V high-speed SRAMs, two proposals are demonstrated. One is a multi-power-supply five-transistor cell (5T cell), combined with a boosted word-line voltage and a mid-point sensing enabled by precharging bit-lines to VDD/2. The other is a partial activation of a multi-divided open-bit-line array without significant area penalty. Layout and postlayout simulation with a 28-nm fully-depleted...
In this paper we present implementation of a 32-bit adder using Quad Carry Look Ahead(QCLA) algorithm in compound domino logic with Merged Pre-charge Keeper transistor and Statistically Skewed Inverter with Double Gate MOSFET(DGMOSFET)s. The worst case propagation delay of the adder is 220ps. The average operating power is 186 µW.
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