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This paper presents a scheme of 14-bit 100MS/s pipelined analog-to-digital converters (ADCs) with digital calibration. Signal-dependent pseudo-random dithering has been used in the proposed model to measure the errors caused by finite gain and capacitors mismatch in multiplying digital-to-analog converters and correct them in the digital domain. Comparing with fixed-magnitude PN dithering, a signal-dependent...
The power supply rejection (PSR) based on closed-loop low-dropout regulator (LDO) is analyzed to achieve high PSR in LDO, and help the designer meet the PSR requirement when considering the other performances of LDO. Using small signal model of MOS transistor, Kirchhoff's current/voltage law, and the tool of Mathematica, the PSR with DC gain, poles, and zeros of power stage and six kinds of basic...
This paper describes a digital calibration scheme for pipelined analog-to-digital converters (ADCs). The proposed method corrects the nonlinearity caused by finite gain and bandwidth of interstage operational amplifiers as well as the capacitors mismatch in multiplying digital-to-analog converters. The proposed calibration technique takes the advantages of both foreground and background calibration...
This paper presents the behavioral models for operational amplifier (opamp) by using analog hardware description language, Verilog-A. The Opamppsilas behavioral model is built with limited unit-gain bandwidth, slew-rate and nonlinear gain. A hyperbolic tangent model has been used to describe the nonlinearity of the Opamppsilas gain, which provides the error less than 0.26% against the transistor-level...
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