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This paper presents an enhanced voltage reference for Switched-Capacitor ADCs. Charge losing effect is analyzed and quantized. Charge-Compensation-Based (CCB) technique is introduced to reduce the signal-dependent effect. Charge Compensation Unit (CCU) is designed to compensate charge. It features in low overhead on power and chip-size. A proof-of-principle CCB reference design for a 12-bit 500MS/s...
This paper presents a dual-channel 11-bit 200MS/s hybrid SAR ADC IP. Each channel adopts flash-SAR architecture for high speed, low power and high linearity. Dynamic comparators in the coarse flash ADC and the fine SAR ADC further contribute to the reduction of power consumption. A gate-controlled ring oscillator generates a multi-phase clock for SAR logic, thereby allowing it asynchronously triggers...
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