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The channel temperature rise is demonstrated due to self-heating in narrow tri-gate fully depleted silicon-on-insulator devices becomes inaccurate when extracted using the gate resistance thermometry. Thermal resistance and channel temperature have been extracted by both gate resistance measurements and 3D TCAD electrothermal simulations for tri-gate wide and nanowire MOSFETs down to 12.5 nm fin width...
The paper presents an overview of the Bias Temperature Instabilities (BTI) reliability in High-k/Metal gate technologies. We show that mobility performance and NBTI reliability are strongly correlated and that they are affected by the diffusion of nitrogen species N at the Si interface. PBTI, more sensitive to bulk oxide traps, is strongly reduced in very thin dielectric films. Reducing the metal...
In this work, we present a detailed investigation of the electrical characteristics of 3D Gate-All-Around (GAA) Silicon nanowire (down to 6nm-diameter) SONOS memories compared to standard planar SONOS devices. In particular, by means of TCAD simulations, the write, erase and retention characteristics under uniform FN stress are explained and the main geometrical and electrostatic effects of 3D cylindrical...
The extraction of the trap density on Ge/gate-stack (top) and Ge/BOX (bottom) interfaces of germanium-on-insulator pMOSFETs is shown using the Lim & Fossum model historically developed for fully depleted SOI devices. The doping and the thickness of the Ge film do not change significantly the top interface trap density. The bottom one is slightly raised by doping the Ge film. This method can be...
A systematic study of mobility performances and BTI reliability was done in advanced dielectrics stacks. By reducing the oxide films thicknesses THKles2.5 nm, PBTI becomes generally very low and associated lifetimes are always over 10 years. By studying a large variety of dielectric stacks we also clearly demonstrate that mobility performances, interface defects Nit and NBTI reliability are strongly...
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