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In this paper, we propose a new PLL frequency synthesizer utilizing multi-programmable dividers which can attain a higher speed lock-up time. Proposed PLL can increase the loop gain without the increase of reference frequency. Effectiveness of PLL with multi-programmable dividers and multi-phase detectors will be shown by the theoretical considerations and experimental results.
In this paper, we propose a DSP type Frequency Locked Loop (DSP-FLL) using a Frequency Difference Detector (FDD). Since the FDD is employed, the DSP-FLL is controlled by the frequency. Therefore, the transfer function becomes first order and ringing does not occur. Furthermore, it can be understood from the detection property of the FDD that the cycle slip does not occur and DSP-FLL can pull in the...
In this paper, we propose a new speedup method of frequency switching time of the prescaler PLL frequency synthesizer using $$(N + \tfrac{1}{2})$$ pulse swallow programmable divider. The $$(N + \tfrac{1}{2})$$ pulse swallow programmable divider can set half the division ratio $$(\tfrac{D}{2})$$ in comparison with the desired division ratio D. In the improved prescaler method, since...
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