Search results for: Hyunik Kim
article
IEEE Journal of Solid-State Circuits > 2017 > 52 > 11 > 2934 - 2946
In this paper, we propose a low-jitter low-power digital multiplying delay-locked loop (MDLL) with a self-calibrated double reference injection scheme. To reduce jitter, the noisy edge of the oscillator is replaced by both the rising and falling edges of the clean reference, which results in 6-dB reduction in phase noise compared with a conventional single-edge injection MDLL. Reference spur caused...
chapter
A multiplying delay-locked loop (MDLL) is an attractive architecture for a low-jitter clock generator, as it does not suffer much from jitter accumulation [1–4]. By periodically replacing the output edge of the oscillator by a clean edge of the reference, an MDLL has a large effective loop bandwidth for oscillator phase noise, which cannot be obtained in a PLL. With this advantage in mind, several...
chapter
Since the advent of digital PLLs (DPLLs), various techniques have been proposed fora low-power, low-noise fractional-N frequency synthesizer. Among the various innovations, a reference-multiplied architecture offers distinct advantages compared to conventional DPLLs [1]. First, low quantization noise (q-noise) can be achieved without complex q-noise cancellation schemes, since the delta-sigma modulator...
article
Journal of the Korean Physical Society > 2012 > 60 > 1 > 155-158
The optical trapping efficiency of optical tweezers can be explained by the ray optics model when the particle size is much larger than the wavelength of laser light. The Optical trapping efficiency in the ray optics model does not depend on the particle size. However, The most experimental results usually show that the optical trapping efficiency decreases as the particle size decreases. In this...
