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With increasing clock frequencies and resolution requirements in mixed-mode telecom circuits substrate noise is becoming more and more a major obstacle for single chip integration. At higher frequencies, the substrate noise is not scaling with the clock frequency anymore, especially when ringing occurs in the spectrum of the supply current transfer function to the substrate. In this paper, we propose...
This paper presents a closed design plan for high accuracy current steering D/A converters. All the steps in the design, from topology choice to the dimensioning of the D/A core, are covered, including the influence of random and systematic errors on the D/A converter's performance. Also, the necessity of a well considered layout is pointed out. To achieve the high accuracy performance, the matching...
This paper presents an algorithm for the performance driven placement of temperature sensitive analog integrated circuits. A simulated annealing algorithm is used to optimize ah initialy random placement. During each iteration of the optimization algorithm, the temperature distribution caused by power dissipating devices is calculated using an analytical multi-layer thermal model. The influence of...
This paper presents a new approach towards performance-driven placement of analog circuits. A simulated-annealing algorithm is used to drive an initial solution to a placement that respects the circuit's performance specifications. During each iteration, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool handles...
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