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This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-on capture (LOC) scheme followed by the one-hot LOC scheme for testing delay faults in a scan design containing asynchronous clock domains. Typically, the staggered scheme produces small test sets but needs long ATPG runtime, whereas the one-hot scheme takes short ATPG runtime but yields large...
A modified loop filter structure for symbol synchronizer with reduced timing jitter is proposed. A moving average unit (MAU) is added to the traditional proportional-integral (PI) structure to form the modified loop filter. Since the variance of the noise is limited under the average operation, timing jitter is reduced efficiently. Furthermore, the structure is easy for implementation, which requires...
An earlier paper [1] introduced the theory of the single-symbol parallel interpolation in all-digital receiver, in which the interpolation is based on a scale of symbol, characterized by vector-operation of the vector input, fractional delay, and output. In this paper, the theory of the multiple-symbol parallel interpolation in all-digital receiver is proposed, in which the interpolation is based...
In this paper, a parallel interpolation structure for all-digital receiver is proposed. Unlike the existing serial interpolation method, which makes timing-adjustment for one sample at a time, the single-symbol parallel interpolation makes timing adjustment for one symbol at a time. This trait lightens the hardware-constraint to the processing rate of the interpolator, and in turn, improves the processing...
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