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A method of feature selection using elitist Genetic Algorithm is proposed in this work. Stratified-tenfold-cross-validation classification accuracy is used as fitness function. The method developed can detect redundant and irrelevant features, consequently producing the optimal feature set. The algorithm is carried out on the four benchmark datasets. Results of the experiments carried out shows that...
The process of testing Integrated Circuits involves a huge amount of data: electrical circuit measurements, information from wafer process monitors, spatial location of the dies, wafer lot numbers, etc. In addition, the relationships between faults, process variations and circuit performance are likely to be very complex and non-linear. Test (and its extension to diagnosis) should be considered as...
We make the case that TDF timing tests, even when aggressively applied at-speed, uniquely detect mostly open defects within standard cells. The majority of these defects can also be detected at somewhat slower test speeds without the risk of unnecessary yield loss from test noise. Meanwhile, many other opens that can cause operational failures remain undetected by current LOC, and even LOS, TDF tests...
Scan based transition delay fault (TDF) tests are generally applied in the launch-on-capture (LOC) mode because the scan enable control signal broadcast to all flip-flops on the die is expensive to implement as a fast switching signal needed to support at-speed launch-on-shift (LOS) tests. However, there is mounting evidence that even when applied at much slower speeds, LOS tests often detect a significant...
Scanning of test vectors during testing causes unnecessary and excessive switching in the combinational circuit compared to that in the normal operation. In this paper, we propose a modified design of a scan flip-flop which eliminates the power consumed due to unnecessary switching in the combinational circuit during scan shift, with a little impact on performance. The new scan flip-flop disables...
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