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This brief presents an energy-efficient high-speed digital-to-analog converter structure that is implemented in a 10-bit 150-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). To reduce energy consumption and improve ADC linearity, a segmented prequantize and bypass architecture is proposed to avoid unnecessary switching of high-weight capacitors based on the results of...
This paper presents an energy efficient high speed DAC structure that is implemented in a 10-bit 150MSample/s successive approximation register (SAR) ADC. To reduce energy consumption and improve ADC linearity, a segmented pre-quantize and bypass architecture is proposed to avoid unnecessary switching of high-weight capacitors based on the results of pre-quantization. Time required for one bit cycling...
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