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Aging and soft errors have become the two most critical reliability issues for nano-scale CMOS circuit. First, in this paper, the aging effect due to bias temperature instability (BTI) is analyzed on different logic gate using 45nm Technology, and simulated the critical charge and delay which can influence soft error rate (SER) result. Second, a method of SER calculation considering BTI effect is...
Metallic carbon nanotubes (m-CNs) cause malfunction by shorting the source and drain terminals in carbon nanotube transistors. To achieve high-yield with robust read and write operations, a new nine carbon nanotube MOSFET (9-CN-MOSFET) static random-access memory (SRAM) cell that can tolerate the removal of m-CNs is proposed in this paper. A functional yield model considering the spatial correlations...
Silicon interposer based 2.5D IC is a promising solution for providing low interconnect delay, high bandwidth, and heterogeneous integration. It has been considered as an alternative of the 3D technology. However, testing is a big issue in 2.5D IC. This paper presents a new contactless testing mechanism for pre-bond interposer testing. Our testing mechanism attempts to detect a defective interposer...
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