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High Efficiency Video Coding (HEVC) is new video coding standard beyond H.264/AVC. In this paper, an area and throughput efficient 2-D IDCT/IDST VLSI architecture for HEVC standard is presented. Adopting proposed data flow scheduling and shared constant multiplication structure, the architecture supports variable block size IDCT from 4×4 to 32×32 pixels as well as 4×4 pels IDST. Using 65nm technology,...
High Efficiency Video Coding (HEVC) is the currently developing video coding standard by the MPEG and ITU organizations. Unlike previous video codec standards, HEVC employs variable block size integer DCT/IDCT to conduct spatial redundancy compression. In this paper, a novel 2-D IDCT VLSI architecture for HEVC standard is presented. Using adaptive block size scheduling scheme, the proposed architecture...
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