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With an increasing number of complex cells in today's VLSI designs, intra-gate opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOF) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient...
Opens are known to be one of the predominant defects in nanoscale technologies. Especially with an increasing number of complex cells in today's VLSI designs intra-gate opens are becoming a major problem. The generation of tests for these faults is hard, as the timing of the circuit needs to be considered accurately to prevent the invalidation of the generated tests through hazards. Current test generation...
Recent studies indicate that a significant number of very large delay faults that increase circuit path delays several fold, remain difficult to detect and are only discovered by very carefully crafted and comprehensive two-pattern tests, e.g. cell aware tests. A likely source of such large delays in CMOS is stuck-open faults. These can sometimes still allow the circuit to reach the correct logic...
In this paper, we focus on the detection of small gate-oxide defects, which can escape production tests but lead to early-life-failures (ELF) during normal operation. Very-Low-Voltage (VLV) and MinVDD testing have been proposed in the past to screen such “weak” ICs. However, small defects that are not severe enough to trigger logic failures can still escape such tests given the fact that power supply...
End-of-road map CMOS (<=10nm) technology is expected to display extreme random variability in device parameters, resulting in a very large spread in the speed of individual gates. Based on reasonable statistical estimates, virtually every large circuit in this environment can be expected to contain several extremely slow statistical outlier gates which will severely limit performance in synchronous...
Providing carry completion signaling in low cost ripple carry adders can allow the control logic to schedule the next addition as soon as an earlier one is complete, thereby achieving the average case, rather than worst case addition delay over a set of computations. Earlier attempts at using current sensing for such carry completion signaling suffered from serious limitations. In this paper we present...
Testing using a random access scan (RAS) design-for-test approach is experiencing renewed interest because of the potential for lower test application time, low power dissipation, and low test data volume compared to standard serial scan. In this paper we propose a significant modification and enhancement to the T-Flip-Flop based cell design for Random Access Scan (RAS). Importantly, the new RAS cell...
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