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High-speed electronic integrated circuits are essential to the development of new fiber-optic communication systems. Close integration and co-design of photonic and electronic devices are becoming more and more a necessity to realize the best performance trade-offs. This paper presents our most recent results and a brief introduction to our research in recently started EU projects.
An ultra-low power SiGe BiCMOS IC for driving a 10 channel EAM array at 113 Gb/s is presented for WDM-PON applications. The driver array consumes only 2.2 W or 220 mW per channel, 50% below the state of the art.
We present a first high performance APD-based linear burst-mode receiver (BM-RX) with a record wide dynamic range of 31dB. The APD multiplication factor is controlled from burst to burst within 60ns by an on-chip self-generated M-control signal.
This paper reports a high performance DC-coupled 10Gbit/s optical burst-mode receiver for symmetric 10G-GPONs. The measured receiver sensitivity is −30.0dBm at BER=10−3 within a short settling time of 51ns, and a loud/soft ratio wider than 24.0dB.
The paper gives an overview of burst-mode receiver developments. The receiver design challenges associated with high speed TDMA PONs are discussed and recent results of 10Gb/s burst-mode receivers are highlighted.
Accurate indoor positioning is very challenging. At this time, no solutions exist that can offer accurate distance measurements over large ranges. In this paper, we present a novel ranging technique. It offers sub-meter accuracy in indoor environments and can maintain this accuracy over hundreds of meters. Currently, this ranging technique has been demonstrated with a dedicated PCB implementation...
We present a 10 Gb/s burst-mode receiver featuring automatic reset generation. The measured sensitivity is -12.5 dBm at a loud/soft ratio of 11.5 dB with a guard time of 25.6 ns and a short preamble of 23.8 ns.
Today's broadband access is moving towards PONs at 10Gb/s. This requires a burst-mode receiver to support the TDMA protocol used in its upstream path. Such a receiver consists of a burst-mode transimpedance amplifier (BM-TIA) which largely dictates the performance of the receiver and a burst-mode post-amplifier (BM-PA) that removes all dc-offsets present in the BM-TIA signal and regenerates the logical...
In this paper we research an FPGA based application specific instruction set processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable compilation flow. The toolchain is used to develop an initial processor design, asses the performance and identify the potential bottlenecks. A second design iteration results in a fully optimized ASIP with a VLIW instruction...
A low cost embedded OTDR method is presented for monitoring the fiber plant of TDM optical networks without extra optical components nor performance penalty. It localizes abrupt changes in link attenuation without disturbing network operation.
This paper presents a feasible set of analog ASIC requirements optimized to achieve co-existence in a broadband power line communications (PLC) system based on frequency division multiplexing (FDM). FDM is the most straightforward way to achieve co-existence between different systems, however, this involves many design challenges at the circuit level. First, a short description will be given of the...
This paper presents the effective optical gain achieved with FEC in 1.25 Gbit/s GPON uplink yielding -36 dBm burst-mode receiver sensitivity and 25 dB dynamic range. A low cost embedded fiber monitoring system measures fiber attenuation and locates deteriorations without interference with TDM(A) network operation or power budget penalty. Finally, a 10 Gbit/s WDM/TDMA long reach PON system is introduced
In this paper we research an FPGA based application specific instruction set processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an architecture optimized to handle flow processing tasks such as parsing, classification and packet manipulation. The VLIW instruction set allows for high degree of parallelism among the functional units inside the ASIP and has...
This paper describes a digitally controlled on-chip monotonic reference current generator with 8-bit resolution and a LSB (least significant bit) current as low as 100 nA. It was designed as a building block of a generic DC-coupled burst mode laser diode driver (BM-LDD) for GPON (gigabit passive optical network) applications and acts as an on-chip reference current generator with a settling time of...
In this paper, a reconfigurable platform for the real-time digital emulation of copper access networks is presented. The instrument, using hard real-time DSP techniques on Xilinx Virtex II FPGAs, is capable of accurately reproducing the physical layer of a xDSL connection. The magnitude and absolute phase of the insertion and return loss of the twisted pair access loop consisting of cables with various...
A multi-channel optical link based on the fiber-in-board technology is presented. It is built with LD-transmitter and PIN-receiver modules of surface mount type, and re-configurable ribbon optical connectors based on fiber optical taps. Experiments show a bit rate up to 622 Mb/s per channel at a density of 4 fibers per millimeter, for both an on-board link and off-board link.
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