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A real-time FPGA-based receiver of 21Gb/s PS-QPSK signal is reported and tested against optical noise, chromatic dispersion (CD), polarization mode dispersion (PMD) and state of polarization (SOP) scrambling. A comparison with PDM-QPSK realized with equivalent parameterized setup and signal processing confirm the greater tolerance of PS-QPSK over PDM-QPSK.
We report the experimental transmission of 4-D coded modulation formats based on set-partitioning of two 16QAM 2-D constellations. Using Nyquist-pulse-shaping, 32SP-DP-16QAM and 128SP-DP-16QAM signals are transmitted over long-haul distance and compared with PDM-16QAM.
We present the first prototype of a real-time bandwidth-variable coherent muxponder aggregating multiple 10GigE clients onto a symbol-rate-variable PDM-QPSK optical signal. This technology enables optical transport with power consumption linearly proportional to the actual requested traffic.
We experimentally show a real-time coherent receiver operated in burst mode. Enabled by special headers, 28-Gb/s PDM-QPSK packets with random states of polarizations are successfully demodulated, and the sensitivity to optical noise is reported.
A fully reprogrammable coherent receiver using an integrated coherent front end, four high speed ADCs and powerful FPGAs is reported and tested against optical noise level, chromatic dispersion and PMD for various equalizer filter length.
We compare set partitioned two-polarization 16QAM formats with conventional PDM-QPSK and PDM-8QAM formats by considering error correction coding. We particularly show that 128SP-16QAM appear as a competitive alternative to PDM-8QAM for spectrally efficient (>4 b/s/Hz) optical transmission systems using forward error-correction coding.
We achieve full real-time operation of 28 Gb/s burst-mode PDM-QPSK coherent receiver capable of handling packet-to-packet jitter and polarization wandering. The receiver is demonstrated with subwavelength switching in a four-node WDM optical packet network testbed.
In this paper, we propose and study a new family of error-correcting codes. These achieve excellent error performance under an iterative decoding over the binary-input noisy channel and solves the memory space requirements problem of the non-binary LDPC decoders. We named this class of codes, Split non-binary LDPC codes. The main particularity of this new family of codes is that the variable and the...
In this paper, we propose a hardware implementation of the EMS decoding algorithm for non-binary LDPC (NB- LDPC) codes, presented in [4]. To the knowledge of the authors this is the first implementation of an GF(q) LDPC decoder for high order fields (q ges 64). The originality of the proposed architecture is that it takes into account the memory problem of the NB-LDPC decoders, together with a significant...
In this paper, we propose a hardware implementation of the EMS decoding algorithm for non-binary LDPC codes, presented in [10]. To the knowledge of the authors this is the first implementation of a GF(q) LDPC decoder for high order fields (q ges 64). The originality of the proposed architecture is that it takes into account the memory problem of the non-binary LDPC decoders, together with a significant...
In this paper, we propose a new implementation of the EMS decoder for non binary LDPC codes presented in (D. Declencq and M. Fossorier, 2007). A particularity of the new algorithm is that it takes into accounts the memory problem of the non binary LDPC decoders, together with a significant complexity reduction per decoding iteration. The key feature of our decoder is to truncate the vector messages...
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