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An off-chip calibration technology for the 6 Bit 30 Gsps time-interleaved ADC is presented in paper. The mismatches errors are calculated by calibration algorithm base on statistical approximation method. Negative feedback is used to reduce the three mismatches (skew, offset and gain mismatch). The off-chip calibration technology is implemented by FPGA. The measured results show that the average ENOB...
A five-stage W-band low-noise amplifier (LNA) based on the authors' InP/InGaAs double heterojunction bipolar transistors (DHBTs) process is reported. The LNA achieves a peak gain of 33.1 dB and 7.8 dB noise figure at 81GHz. Its output-related 1 dB compression point (P1dB) lies at 5.8 dBm. The high gain and linearity of the LNA is mainly attributed to the performance of the DHBTs exhibiting a high...
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