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This brief presents an energy-efficient high-speed digital-to-analog converter structure that is implemented in a 10-bit 150-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). To reduce energy consumption and improve ADC linearity, a segmented prequantize and bypass architecture is proposed to avoid unnecessary switching of high-weight capacitors based on the results of...
A 14-b 100-MS/s pipeline analog-to-digital converter (ADC) is presented. The ADC uses six 4-b stages with 2-b interstage redundancy to relax the requirements of Sub-ADC nonlinearity and interstage offset. The ADC, implemented in a 0.18-μm CMOS process, achieves 70.3-dB signal-to-noise and distortion ratio (SNDR), 83.7-dB spurious free dynamic range (SFDR) and 11.3 effective number of bit (ENOB) with...
This paper presents an energy efficient high speed DAC structure that is implemented in a 10-bit 150MSample/s successive approximation register (SAR) ADC. To reduce energy consumption and improve ADC linearity, a segmented pre-quantize and bypass architecture is proposed to avoid unnecessary switching of high-weight capacitors based on the results of pre-quantization. Time required for one bit cycling...
This paper presents a high speed parallel segmented capacitive DAC that is implemented in a 10-bit 150MSample/s successive approximation register (SAR) ADC. Compared to converters that use the conventional structure, the speed of converting one bit digital code can be 4 times faster while the power remains relatively low. In the switching procedure, a small capacitor array is used to determine the...
In order to reduce the design difficulties, the input sample-and-hold amplifier (SHA) is often removed in the nested background calibration of the CMOS pipelined analog-to-digital converters (ADC). The system uses a dual-channel LMS adaptive digital background calibration algorithm, and the reference ADC was calibrated in the foreground. Without the input SHA, the sampling-time error between the two...
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