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Along with advances in modern VLSI technology, delay faults are becoming ever more important. On the other hand, the strength of SAT-solver engines has made them an attractive means for solving many Computer Aided Design (CAD) problems. This paper presents a new SAT-based Automatic Test Pattern Generation (ATPG) approach targeting transition delay faults using a novel 8-value encoding system. Experimental...
Fault diagnosis is one of the most important phases in the VLSI design cycle. This paper proposes a probabilistic solution for the fault diagnosis in the sequential scan-based circuits. Our approach uses a signal probability analysis to score and rank potential fault locations. The ranking results are exploited to reduce the search space for exact diagnosis approaches. The experimental results show...
By advances in technology, integrated circuits have come to include more functionality and more complexity in a single chip. Although methods of testing have improved, but the increase in complexity of circuits, keeps testing a challenging problem. Two important challenges in testing of digital circuits are test time and accessing the circuit under test (CUT) for testing. These challenges become even...
In this paper we propose to think out of the box and discuss an approach for universal mitigation of Negative Bias Temperature Instability (NBTI) induced aging untied from the limitations of its modelling. The cost-effective approach exploits a simple property of a randomized design, i.e., the equalized signal probability and switching activity at gate inputs. The techniques considered for structural...
This paper proposes a technique for reducing power consumption and increasing pipeline performance using the state of art “Better than worst case” design. This method uses a violation predication mechanism that places the optimum number of Transition Detectors and a novel Time Borrowing technique to prevent potential timing errors. In this work the tradeoff between power consumption (Transition Detectors...
In this paper, we introduce a new technique that makes use of satisfiability (SAT) based debugging techniques along with a mutation-based technique to correct certain design errors in digital designs automatically. The experimental results demonstrate that our proposed method enables us to locate and correct multiple bugs by targeting gate replacements and wire exchanging within reasonable run-time...
This paper discusses a set of functions which are added to Verilog through its PLI interface that facilitates test and application of test programs to designs at the RT level. Using this package, not only enables a designer to apply test programs to RTL designs, but also takes advantage of RTL simulation of abstract HDL descriptions for speeding up test programs. The package proposed here eliminates...
This paper introduces a complete test package in VHDL that makes it possible to simulate faults and generate test patterns for a component during its design process. Different approaches on test applications can be combined and then be applied to combinational, sequential and scan-based circuits in a fully configurable and convenient environment. To reveal the capabilities of VHDL in test configurations,...
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